As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as a fin field effect transistor (FinFET). A typical FinFET is fabricated with a thin vertical “fin” extending from a substrate formed by, for example, etching away a portion of a silicon layer of the substrate or epitaxial layers grown on the substrate. The channel of the FinFET is formed in this vertical fin. A gate is provided over (e.g., wrapping around) the fin.
Fabricating a FinFET is not without its own challenges. For example, it is desirable to decrease the distance between a fin in an n-type field effect transistor (nFET) region and a fin in a p-type FET (pFET) region to increase device density. However, when the distance is decreased to a certain level, it becomes difficult to make a clean gate cut to separate dummy gate over a fin in the pFET region and a fin in the nFET region without damaging the epitaxial source/drain features. In some severe cases, epitaxial source/drain features can be substantially etched away in the course of a gate cut, causing device failures.
Therefore, although existing FinFET devices have been generally adequate for their intended purposes, they have not been satisfactory in every aspect.